Date of Award
Electrical and Computer Engineering
Jullien, G. A.
Engineering, Electronics and Electrical.
CC BY-NC-ND 4.0
This thesis presents an improved VLSI architecture to perform different arithmetic operations, multiplication, division and square rooting, along with addition and subtraction. The architecture is highly regular, requires only three control bits to choose among five different operations. Through the use of a redundant binary number system and pipelining, the execution time for each operation is identical and is independent of the wordsize of the array. Moreover, the improved architecture is capable of being implemented using the dynamic switching tree technique. Finally, the improved architecture has been designed utilizing a 0.8 micron BiCMOS technology and has a throughput rate of 100 Megasamples per second for each operation.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1993 .C453. Source: Masters Abstracts International, Volume: 32-02, page: 0678. Adviser: G. A. Jullien. Thesis (M.A.Sc.)--University of Windsor (Canada), 1993.
Chan, Henry Hin Hai., "BiCMOS implementation on DSP arithmetic blocks." (1993). Electronic Theses and Dissertations. 1295.