Bit-parallel word-serial polynomial basis finite field multiplier in GF(2(233)).
Date of Award
Electrical and Computer Engineering
Engineering, Electronics and Electrical.
CC BY-NC-ND 4.0
Smart card gains extensive uses as a cryptographic hardware in security applications in daily life. The characteristics of smart card require that the cryptographic hardware inside the smart card have the trade-off between area and speed. There are two main public key cryptosystems, these are RSA cryptosystem and elliptic curve (EC) cryptosystem. EC has many advantages compared with RSA such as shorter key length and more suitable for VLSI implementation. Such advantages make EC an ideal candidate for smart card. Finite field multiplier is the key component in EC hardware. In this thesis, bit-parallel word-serial (BPWS) polynomial basis (PB) finite field multipliers are designed. Such architectures trade-off area with speed and are very useful for smart card. An ASIC chip which can perform finite field multiplication and finite field squaring using the BPWS PB finite field multiplier is designed in this thesis. The proposed circuit has been implemented using TSMC 0.18 CMOS technology. A novel 8 x 233 bit-parallel partial product generator is also designed. This new partial product generator has low circuit complexity. The design algorithm can be easily extended to w x m bit-parallel partial product generator for GF(2m).Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .T36. Source: Masters Abstracts International, Volume: 43-01, page: 0286. Advisers: H. Wu; M. Ahmadi. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004.
Tang, Wenkai., "Bit-parallel word-serial polynomial basis finite field multiplier in GF(2(233))." (2004). Electronic Theses and Dissertations. 1310.