Date of Award
Electrical and Computer Engineering
Jullien, G. A.
Engineering, Electronics and Electrical.
CC BY-NC-ND 4.0
This dissertation presents a novel architectural technique for systolic architectures for applications which traditionally use high wire organizations in VLSI. Following a review of current VLSI research and VLSI models, this dissertation argues for a particular computational model (Chazelle's model) as being appropriate for today's VLSI and ULSI technology. Systolic arrays are particularly suited for applications where only local interprocessor communication of data is required. In areas where non local data communication is predominant, the so called "high wire organizations" are traditionally used. Such networks include sorting arrays, interconnection arrays. Using Chazelle's model, an analysis of well known interconnection networks shows that "inefficient" systolic arrays, for routing and for sorting, outperform, so far as asymptotic performance metrics are concerned, high wire organizations traditionally used for such applications. This dissertation then proposes a new systolic architecture using the novel design philosophy of locally long but globally short connections. This involves designing arrays using large, complex cells instead of fine grained cells. This is termed "systolic architectures using cells of controllable complexity" since the latency and/or pipeline period requirement of a user determines the size and hence the interconnection complexity of the cells in a systolic array of complex cells. It turns out that many important application areas (e.g., interconnection networks, sorting networks and FFT) are suitable candidates for this approach. This class of architectures is well suited for ULSI implementation. An experiment in designing interconnection networks show that this concept of arrays using cells of controllable complexity is useful, even in current 1.2$\mu$ VLSI technology.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1992 .P358. Source: Dissertation Abstracts International, Volume: 53-12, Section: B, page: 6471. Co-Supervisors: G. A. Jullien; D. Bandyopadhay. Thesis (Ph.D.)--University of Windsor (Canada), 1991.
Panneerselvam, Gopal., "Communication architectures for single-chip data routers." (1991). Electronic Theses and Dissertations. 1481.