Date of Award

2000

Degree Type

Thesis

Degree Name

M.A.Sc.

Department

Electrical and Computer Engineering

First Advisor

Soltis, J. J.,

Keywords

Engineering, Electronics and Electrical.

Rights

CC BY-NC-ND 4.0

Abstract

The DCT block transform is used every day in the compression of images, video and audio for the transmission of television signals, multimedia graphics, audio and video all over the world. Image compression is the efficient coding of digital images to reduce the number of bits required, to represent an image, while maintaining a quality image. Data compression is the transmission of data over communication channels in an effective manner that uses as few bits as possible to minimize the bandwidth required, while maintaining distortions within limits. The efficient implementation of the DCT block in sub-micron CMOS continues to be dependent on the degree of regularity of the chip's architecture. Whereas the chip's required speed is dependent on the degree of parallelism of the DCT transform algorithm-architecture. That is, the speed of the block DCT chip is dependent on the subband signals maintaining a parallel FIR filter bank form. The block DCT transform is efficiently implemented when all the multiplication operations are removed from the architecture, thus minimizing the size of the chip. This thesis deals with the VLSI implementation of a multiply free approximate DCT architecture. The approximate DCT has the capability of mapping integers to integers in sub-micron CMOS with near perfect reconstruction. The approximate DCT is based on the algorithm-architecture found in [11], the binDCT. The forward binDCT chip and inverse binDCT chip designs assume the use of image data as their input. The use of an image as the input signal places the constraint that the chip is to be designed to implement unsigned binary arithmetic. Source: Masters Abstracts International, Volume: 39-02, page: 0561. Adviser: J. J. Soltis. Thesis (M.A.Sc.)--University of Windsor (Canada), 2000.

Share

COinS