Date of Award
1999
Publication Type
Doctoral Thesis
Degree Name
Ph.D.
Department
Electrical and Computer Engineering
Keywords
Engineering, Electronics and Electrical.
Supervisor
Ahmadi, M.
Rights
info:eu-repo/semantics/openAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Abstract
This dissertation is concerned with testing of asynchronous circuits. Asynchronous circuits are attracting increasing interest for future generations of high-speed low-power logic circuits because they facilitate concurrent computation, offer average-case performance and better technology migration potential, and eliminate clock skew. The research reported in this dissertation is a comprehensive study of testing asynchronous circuits using design-for-testability (DFT) techniques and test generation algorithms. In the first part of the study we propose an on-line DFT technique for detecting short defects (or IDDQ faults), which create a low-resistance path between the supply lines. It is shown that I DDQ testing, delay testing, and stuck-open testing are necessary in order to achieve a high defect coverage. The second DFT technique presented in this part is a novel circuit for concurrently detecting delay faults and stuck-open faults. In the proposed DFT techniques, in particular, fault detection in CMOS logic family is investigated. The second half of this study attempts to derive test sequences for sequential circuits. First, initialization phase is studied. Initialization is the process of driving the state signals in the circuit to known states. This dissertation presents an initialization technique for non-initializable asynchronous sequential circuits. Finally, we proceed by generating test sequences for asynchronous sequential circuits. We assume the presence of all multiple faults of all multiplicities. No faulty machines are generated during these procedures and we do not resort to their explicit enumeration.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1999 .R33. Source: Dissertation Abstracts International, Volume: 61-09, Section: B, page: 4897. Adviser: Majid Ahmadi. Thesis (Ph.D.)--University of Windsor (Canada), 1999.
Recommended Citation
Raahemifar, Kaamran., "Testing asynchronous logic circuits from transistor networks to gate-level designs." (1999). Electronic Theses and Dissertations. 3735.
https://scholar.uwindsor.ca/etd/3735