Date of Award
Electrical and Computer Engineering
Engineering, Electronics and Electrical.
CC BY-NC-ND 4.0
This work represents the author's contributions to a joint effort into the development of switching tree architectures. The work concentrates on concepts of CMOS design and lay-out stressing the optimization of parasitic and interconnect capacitance to increase circuit performance. Practical design techniques are discussed with regards to constructing pad frames and power distribution networks. These concepts are then applied to a set of three cells which trace the development of the switching tree cell. The clocking schemes, ROM architectures and general structure of each cell are discussed in detail. Finally, a set of standard cells is constructed using the switching tree structure, in 3$\mu$ CMOS technology. SPICE simulations indicate that cells performing 3-bit binary addition in one clock cycle are capable of functioning at clock speeds of up to 50 Mhz. Test results confirm the functionality of the cells up to the maximum speed of the Input/Output (I/O)pads, which is approximately 40 Mhz. Due to current I/O pad speed limitations, a set of ECL Compatible I/O pads is developed for use as part of the standard cell library. Simulation results indicate that the pads are capable of operating at speeds above 100 Mhz. Test results confirm the pads operation up to 65 Mhz, which is the maximum speed available from the test equipment. Based on the test results, it is estimated that the maximum speed of the 3$\mu$ ECL Compatible I/O pads is approximately 80 Mhz.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1991 .D456. Source: Masters Abstracts International, Volume: 31-01, page: 0388. Thesis (M.A.Sc.)--University of Windsor (Canada), 1991.
Del Pup, Lino., "The development and application of high-speed digital switching trees for regular arithmetic arrays." (1991). Electronic Theses and Dissertations. 3824.