Date of Award
1991
Publication Type
Master Thesis
Degree Name
M.A.Sc.
Department
Electrical and Computer Engineering
Keywords
Engineering, Electronics and Electrical.
Rights
info:eu-repo/semantics/openAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Abstract
The building of complex logic blocks for either pipelined dynamic logic, differential CASCODE dynamic logic, or differential pass-transistor logic is explored. This was motivated by the recent exploration of ROM cell configuration for dynamic residue arithmetic blocks. Logic blocks were synthesized by programming and minimizing ROMs built from a binary tree of n-channel transistors. This technique uses only 3 graph minimization rules on the ROM structure. This is in contrast to the usual techniques which map minimized boolean functions directly to transistor configurations. This technique may be illustrated by examples from both binary and residue arithmetic blocks, where each evaluation node is driven from 6 or more binary inputs and their complements. The results from comparisons between different techniques show that the switching tree design has inherent advantages in terms of overall design size.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1991 .G765. Source: Masters Abstracts International, Volume: 31-01, page: 0391. Thesis (M.A.Sc.)--University of Windsor (Canada), 1991.
Recommended Citation
Grondin, Roger., "The synthesis and modeling of high speed digital switching trees." (1991). Electronic Theses and Dissertations. 4310.
https://scholar.uwindsor.ca/etd/4310