Date of Award
2015
Publication Type
Master Thesis
Degree Name
M.A.Sc.
Department
Electrical and Computer Engineering
Keywords
CONNECT NoC synthesis tool
Supervisor
Khalid, Mohammed
Rights
info:eu-repo/semantics/openAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Abstract
Rapid growth in the number of IP cores in SoCs resulted in the need for effective and scalable interconnect scheme for system components - Network-on-Chip (NoC). Design and implementation of an NoC from scratch is very time consuming and limits the NoC design space that can be explored. In this thesis we evaluate and compare NoC synthesis tool CONNECT with manually generated NoC design using Altera Quartus II. Three sizes of ring, mesh and torus NoC topologies are used for evaluation based on two metrics: logic resource utilization and maximum clock frequency. For larger NoC sizes manual design provides up to 85% reduction in area utilization. With respect to maximum clock frequency, CONNECT provides superior results for all NoC sizes, providing up to 80% higher clock frequency. These results provide an insight into the area versus frequency tradeoffs when using the CONNECT NoC synthesis tool.
Recommended Citation
Rajamanickam Manokara, Jenita Priya, "Experimental Evaluation of an NoC Synthesis Tool" (2015). Electronic Theses and Dissertations. 5286.
https://scholar.uwindsor.ca/etd/5286