Date of Award

10-15-2015

Publication Type

Doctoral Thesis

Degree Name

Ph.D.

Department

Electrical and Computer Engineering

Keywords

Digit-serial architecture, Finite field multiplier, Low power design, Polynomial basis

Supervisor

Ahmadi, Majid

Supervisor

Wu, Huapeng

Rights

info:eu-repo/semantics/openAccess

Abstract

Elliptic curve (EC) cryptosystem is the most efficient public key cryptographic system used in practice. However, it is still computationally intensive and has high power consumption, compared to non-public key cryptographic computations. Therefore, for the power constrained wireless devices a power efficient EC cryptosystem is required. Finite field multipliers are main building blocks of an EC cryptosystem. Thus, low power finite field multipliers are required for a power efficient EC cryptosystem. In this work, we performed VLSI simulation for several existing digit-serial finite field multipliers using the same field with the same VLSI technology so that an effective comparison of their power efficiency along with other parameters can be made. Only few of the digit-serial finite field multiplier architectures proposed in the literature demonstrated power estimation with different VLSI technology for different field sizes. This makes it difficult to compare their power efficiency. We present a low power design for a digit-serial finite field multiplier in . In the proposed design, factoring technique is used to reduce switching power. Logic gate substitution is also utilized to reduce internal power. Our proposed design along with several existing similar works has been realized on ASIC, and a comparison is made among them. The synthesis results show that the total power consumption is significantly reduced for the proposed multiplier design. Our proposed multiplier design consumes about 27.8% less power than the best existing work in comparison.

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