Date of Award
Electrical and Computer Engineering
ARM, Decoder, FPGA, JPEG, System on Chip, Xilinx
CC BY-NC-ND 4.0
An important feature of today's mobile devices is their ability to capture and display high resolution photos in an acceptable time frame. The vast majority of images are stored on disk using the JPEG codec for compression. With increasing pixel counts on both image sensors and screens, software solutions will struggle in their ability to decode JPEG image data, since they rely solely on increasing CPU power. The need is becoming clearer for hardware acceleration to replace the CPU when decoding large images. This thesis presents a System-on-Chip module that is able to relieve the CPU of the computationally intense task of decoding a JPEG image. This SoC module was developed and tested on an FPGA that features an ARM Cortex A9 and a Xilinx Artix-7 FPGA. The SoC module was able to outperform software running on the onboard CPU by about 4 times, while being more accurate to the original image.
Kyrtsakas, George Gabriel, "An FPGA Implementation of a Custom JPEG Image Decoder SoC Module" (2017). Electronic Theses and Dissertations. 5945.
Available for download on Thursday, April 19, 2018