Title

A high level synthesis of a fibre channel core for a system-on-chip implementation.

Date of Award

2005

Degree Type

Thesis

Degree Name

M.A.Sc.

Department

Electrical and Computer Engineering

Keywords

Engineering, Electronics and Electrical.

Rights

CC BY-NC-ND 4.0

Abstract

A high performance standardized System-on-Chip (SoC ) communication system has been developed as an embedded core. A high level synthesis of a Fibre Channel core has been realized that takes advantage of the performance advantages and specifications associated with the Fibre Channel protocol. A soft IP core of a Fibre Channel port is presented in the form of a register transfer level (RTL) descriptor language which can be implemented in arbitrary target technologies. A full-speed (1.0625 GHz link clock) sign-off quality tape-out of the design in TSMC's 0.18 mum technology has been carried out using a design flow centered on the Cadence SoC Encounter platform. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2005 .K84. Source: Masters Abstracts International, Volume: 44-03, page: 1456. Thesis (M.A.Sc.)--University of Windsor (Canada), 2005.

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