Date of Award
Electrical and Computer Engineering
Khalid, Mohammed (Computer Engineering)
Engineering, Electronics and Electrical.
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This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License.
The Network-on-Chip (NoC) approach for designing (System-on-Chip) SoCs is currently emerging as an advanced concept for overcoming the scalability and efficiency problems of traditional on-chip interconnection schemes. This thesis addresses the design and evaluation of a parameterizable NoC router for FPGAs. The importance of low area overhead for NoC components is crucial in FPGAs, which have fixed logic and routing resources. We achieve a low area router design through optimizations in switching fabric and dual purpose buffer/connection signals. We propose a component library to increase re-use and allow tailoring of parameters for application specific NoCs of various sizes. A set of experiments were conducted to explore the design space of the proposed NoC router using different values of key router parameters: channel width (flit size), arbitration scheme and IP-core-to-router mapping strategy. Area and latency results from the experiments are presented and analyzed.
Brugge, Michael, "Design and Evaluation of a Parameterizable NoC Router for FPGAs" (2009). Electronic Theses and Dissertations. 115.