Date of Award
Electrical and Computer Engineering
Wu, Huapeng (Electrical and Computer Engineering)
CC BY-NC-ND 4.0
In this thesis, a new method for implementing cryptographic hash functions is proposed. This method seeks to improve the speed of the hash function particularly when a large set of messages with similar blocks such as documents with common headers are to be hashed. The method utilizes the peculiar run-time reconfigurability feature of FPGA. Essentially, when a block of message that is commonly hashed is identified, the hash value is stored in memory so that in subsequent occurrences of the message block, the hash value does not need to be recomputed; rather it is simply retrieved from memory, thus giving a significant increase in speed. The system is self-learning and able to dynamically build on its knowledge of frequently occurring message blocks without intervention from the user. The specific hash function to which this technique was applied is Blake, one of the SHA-3 finalists.
Esuruoso, Olakunle, "High Speed FPGA Implementation of Cryptographic Hash Function" (2011). Electronic Theses and Dissertations. 124.