Date of Award


Publication Type

Master Thesis

Degree Name



Electrical and Computer Engineering

First Advisor

Khalid, Mohammed (Electrical and Computer Engineering)


Engineering, Electronics and Electrical.



Creative Commons License

Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License.


Continuing improvements in integrated circuit technology over the past few decades enables increasingly large and complex Systems-on-Chip. Due to the large number of components used, the traditional bus-based interconnect scheme becomes cumbersome and restrictive. Hence, the Network-on-Chip interconnect paradigm becomes appealing due to its many advantages such as scalability and superior performance. Much research remains to be done exploring NoC architectures using real world benchmarks. In this thesis we describe the design space exploration of two major NoC components; a flexible adapter based on the Altera Avalon standard and a parameterizable wormhole router. Two well known NoC architectures, torus and ring, were synthesized for Altera FPGAs using these NoC components. The architectures were compared on the basis of packet latency, area and throughput, using a benchmark application. Simulation results show that the ring architecture gives superior area versus performance tradeoffs for the benchmark used.