Date of Award


Publication Type

Master Thesis

Degree Name



Electrical and Computer Engineering

First Advisor

Chen, Chunhong (Electrical and Computer Engineering)





Creative Commons License

Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License.


It is widely known that the decreasing feature size facilitated vast improvement in semiconductor-based design. The scaling down of MOS transistors has almost come to an end due to the limits dictated by their operating principle. In order to ensure further feature size reduction, the field of single-electronics has been developed. Single Electron Tunnelling (SET) technology offers the ability to control the transport and position of a single or a small number of electrons. This thesis investigates the power optimization of single electron memory based on negative differential conductance (NDC) characteristic. A novel SET-based NDC architecture with multiple peaks in I-V characteristic is introduced. Two specific static random-access memory (SRAM) cells are proposed: (i) a ternary SRAM with a standby power consumption of 0.98nW at logic margin of 270mV and (ii) a quaternary SRAM cell with standby power consumption of 5.06 at a logic margin of 160 mV operating at T=77K.. The read/write operations for the memory cell are briefly discussed. All simulations are conducted using the Monte Carlo method from SIMON tools.