Date of Award


Publication Type

Master Thesis

Degree Name



Electrical and Computer Engineering


Engineering, Electronics and Electrical.



Creative Commons License

Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License.


This thesis continues to extend the investigation of a programmable bit-level systolic cell structure which will be used in the Residue Number System arithmetic processor. In this thesis, several kinds of user-programmable storage cell structures have been studied and compared. In addition, novel programming and refreshing schemes have been introduced. The final design of the new systolic cell, reduces the limitations of the old ROM based BIPSP$\sb{\rm m}$ cell and improves the system level design by programming the cells on the fly. Also included is a report on a new VLSI CAD tool set, which was used in the design of the cell components.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1991 .H655. Source: Masters Abstracts International, Volume: 30-04, page: 1428. Thesis (M.A.Sc.)--University of Windsor (Canada), 1991.