Date of Award


Publication Type

Doctoral Thesis

Degree Name



Electrical and Computer Engineering


Engineering, Electronics and Electrical.


Jullien, G. A.




This thesis presents a new mapping strategy and modified architectures for implementing general purpose inner product computations, using enhanced Fermat ALU theory. The structure is based on a direct product finite polynomial ring mapping of a redundant binary representation of the input data; in effect we exploit the double redundancy of the input representation and the mapped polynomial representation. By exploiting this redundancy, with attendant reductions in coefficient growth due to polynomial multiplication, considerably reduction in the probability of overflow error is achieved. The redundant property of the polynomial map is used to optimize the input data. By allowing a mix of positive and negative coefficients to represent any number, regardless of sign, we can reduce the maximum value of the coefficient by as much as half. This is sufficient to reduce the probability of overflow to acceptable levels using only single modulus computations, with considerable reduction in computational hardware. This thesis demonstrates, for the case of FIR filter inner product applications, that this new approach allows the implementation of reasonable filter lengths using only a Mod 257 ALU. The probability of overflow in the finite field channels is considerably reduced compared to an implementation without the enhanced mapping. This results in less hardware and less power dissipation and, due to the additional binary channel, an increase in the output dynamic range. In terms of the efficacy of this new technique, area and power costs for the 53-tap design have been estimated and a complete floorplan and HDL simulations are presented. Source: Dissertation Abstracts International, Volume: 61-09, Section: B, page: 4899. Adviser: G. A. Jullien. Thesis (Ph.D.)--University of Windsor (Canada), 1999.