Date of Award
Electrical and Computer Engineering
CC BY-NC-ND 4.0
This work presents a new fast and efficient algorithm for a floating point multiplier that adheres to the IEEE 754 standard and also investigates its VLSI implementation. As a verification tool, VHDL is used to simulate the hardware model of the new floating point multiplier algorithm. In addition this work describes and compares several parallel multiplier architectures including a new parallel multiplier architecture which is both time optimal and regular in structure. This new multiplier architecture will be used as part for the new floating point multiplier algorithm. Finally the BICMOS implementation of the new multiplier architecture is discussed.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1992 .M474. Source: Masters Abstracts International, Volume: 31-04, page: 1847. Thesis (M.A.Sc.)--University of Windsor (Canada), 1992.
Mesfin, Biniam., "Implementation of a high performance floating point unit multiplier." (1992). Electronic Theses and Dissertations. 2388.