Investigation into arithmetic sub-cells for digital multiplication.
Date of Award
Electrical and Computer Engineering
Engineering, Electronics and Electrical.
CC BY-NC-ND 4.0
A study of several low-power and high-speed (3,2) counter designs is initially presented, then based on these findings, a new 4:2 compressor design is introduced and proven against other existing and newly devised 4:2 compressors using various logic styles. The results obtained with regards to speed, power and size were used to categorize the circuits in terms of individual and cumulative performance characteristics. A complete 16-bit multiplier design which uses a highly efficient layout scheme along with the top performing 4:2 compressor form the above study is presented. A second multiplier using industry standard (3,2) counters in a 4:2 compressor configuration following the same optimized layout scheme is constructed and simulated as a benchmark for comparison to the new design. In order to carry out this investigation, the proper methodology for power measurement in pass-logic circuits was developed and is presented within. This survey offers an unpartisan approach to power measurement, and an accurate reflection of the vantage points of each logic style. (Abstract shortened by UMI.)Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2005 .H69. Source: Masters Abstracts International, Volume: 44-03, page: 1453. Thesis (M.A.Sc.)--University of Windsor (Canada), 2005.
Howard, G. Michael., "Investigation into arithmetic sub-cells for digital multiplication." (2005). Electronic Theses and Dissertations. 2499.