IP protection for DSP algorithms' FPGA implementation.
Date of Award
Electrical and Computer Engineering
Kwan, H. K.
Engineering, Electronics and Electrical.
CC BY-NC-ND 4.0
With today's system-on-chip (SOC) technology, we are able to design larger and more complicated application-specific integrated circuits (ASICs) and field programmable gate array (FPGA) in shorter time period. The key point of the success of SOC technology is the reuse of intellectual property (IP) cores. Consequently the copyright protection for these IP cores becomes the major concern for the development pace of SOC technology. Watermarking technology has been proved to be an effective way of copyright protection. In this thesis, the author presents two new watermarking algorithms respectively at algorithm level and FPGA layout level. The simulations and implementation results show that the new proposals have much less design and hardware implementation overheads, lower watermark embedding and extraction cost, as well as higher security strength, compared to the previously proposed methods.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .D39. Source: Masters Abstracts International, Volume: 43-03, page: 0929. Advisers: H. K. Kwan; H. Wu. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004.
Dai, Wei., "IP protection for DSP algorithms' FPGA implementation." (2004). Electronic Theses and Dissertations. 2517.