Optimizing power, delay and reliability for digital logic circuits with CMOS and single-electron technologies.

Date of Award


Publication Type

Master Thesis

Degree Name



Electrical and Computer Engineering


Engineering, Electronics and Electrical.



Creative Commons License

Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License.


In this thesis, we present two low power approaches with consideration of delay and/or reliability. The first approach is based on CMOS (Complementary Metal-Oxide Semiconductor) technology. Given a gate level topology of digital circuits and a target library, we propose a greedy algorithm for delay budgeting in order to optimize power dissipation. The algorithm is implemented with JAVA SDK. The developed software tool estimates how much power dissipation (percentage) can be saved without increasing the circuit delay, and the potential of power savings by relaxing the circuit's timing constraints. The second low power approach is proposed with SET (Single Electron Tunneling) technology. We focus on an elementary logic structure called threshold gate, and present a standard procedure of logic implementation, with analysis of delay, power and reliability due to background charge effect. As an application example, an FSM (Finite State Machine) for RFID (Radio Frequency Identification) system is designed and simulated successfully.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2006 .M5. Source: Masters Abstracts International, Volume: 45-01, page: 0418. Thesis (M.A.Sc.)--University of Windsor (Canada), 2006.