Date of Award
1995
Publication Type
Doctoral Thesis
Degree Name
Ph.D.
Department
Electrical and Computer Engineering
Keywords
Engineering, Electronics and Electrical.
Supervisor
Jullien, G. A.
Rights
info:eu-repo/semantics/openAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Abstract
Traditional design of logic circuits involves implementing a function in terms of standard logic gates. However, this type of design does not fully exploit the unique switching properties of MOSFETs, which can lead to more efficient realizations. Over the past decade there has been considerable interest in Pass Transistor Logic (PTL) circuits. PTL circuits implement a logic function as a network of NMOS transistors. They show enhanced performance over conventional logic in terms of both speed and area optimization as well as reduced power dissipation, particularly for certain classes of circuits. Existing synthesis techniques for PTL are limited to two-level synthesis, similar to that used for conventional logic. In conventional logic multilevel logic implementations have been shown to provide significant improvements over two-level representations. So it is of considerable interest to develop formal multilevel design methodologies for PTL in order to exploit potential efficiencies in that circuit family. Such formal design methodologies are also necessary to avoid incorrect implementations which can result from ad hoc design of PTL networks. This thesis deals with the development of methodologies for the systematic design of multi-level PTL networks. In this thesis, we have investigated two approaches to multi-level logic synthesis techniques for PTL networks based on the concepts of (i) factorization and (ii) decision diagrams. Both approaches have shown significant savings over known synthesis techniques for PTL networks.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1995 .J33. Source: Dissertation Abstracts International, Volume: 57-07, Section: B, page: 4602. Co-Advisers: G. A. Jullien; S. Bandyopadhyay. Thesis (Ph.D.)--University of Windsor (Canada), 1995.
Recommended Citation
Jaekel, Arunita., "Synthesis of multilevel pass transistor logic networks." (1995). Electronic Theses and Dissertations. 3699.
https://scholar.uwindsor.ca/etd/3699