Date of Award
Electrical and Computer Engineering
Engineering, Electronics and Electrical.
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This work presents systolic architectures for implementing finite rings and fields operations in VLSI. By decomposing these operations, at the bit level, a generic cell, consisting of a small ROM and ancillary circuitry, can be used to compute most of the commonly used digital signal processing algorithms. Various implementations for modular addition and multiplication, based on this cell, are given and compared to conventional single ROM techniques. The advantages of the new method, from the point of view of saving memory locations, silicon area, and increasing throughput are discussed. The application of the technique in the area of Digital Signal Processing has been investigated. Structures for implementing Finite Impulse Response (FIR) filters, both bit serial and bit parallel, are presented. The design of fixed coefficient FIR filters implemented using Residue Number Systems (RNS) and binary are compared, and it is shown that the RNS approach requires less silicon area and operates at very high speeds. A novel distributed fault detection technique has been introduced. A small amount of extra hardware enables the cell to detect run time faults. It is shown that only one redundant modulus is required to correct errors when this distributed fault detection is used, as opposed to two moduli in conventional Redundant Residue Number Systems (RRNS). The issue of the testability of the fabricated designs has also been addressed, and a simple procedure for testing arrays of these generic cells is proposed which takes advantage of the contents of the ROMs and the capability of by-passing subsections of the array. Source: Dissertation Abstracts International, Volume: 49-04, Section: B, page: 1326. Thesis (Ph.D.)--University of Windsor (Canada), 1988.
Taheri, Majid., "VLSI fault-tolerant systolic architectures." (1988). Electronic Theses and Dissertations. 4536.