Date of Award


Publication Type

Master Thesis


Electrical and Computer Engineering




Logic emulation systems are used to verify the functionality of logic designs targeted for integrated circuit implementation. In this thesis, the design and implementation of a low-cost processor-based logic emulation system is presented. It contains multiple processors interconnected together and packaged in one emulation engine. It is capable of emulating combinational and sequential logic at relatively high speeds of 187 KHz or more, in real operating environments and with predictable compile time. The implementation was done on an FPGA to reduce cost. The proposed system is scalable to a multi-FPGA system where several of these identical FPGAs could be connected together to increase the logic capacity of the system. The architecture and operation of the emulator is first described. Architecture exploration experiments were conducted in order to choose suitable values for different architecture parameters for implementation on the target FPGA. The design was implemented on an Altera Stratix FPGA. A four-bit multiplier was emulated to verify correct operation of the proposed emulation system.