Date of Award


Publication Type

Doctoral Thesis

Degree Name



Electrical and Computer Engineering


Elliptic Curve Cryptography, Finite Field Multiplication, Hardware Implementation


Ahmadi, Majid


Muscedere, Roberto




Cryptography can be categorized into two fundamentally different classes: symmetric-key and public-key (also known as asymmetric-key). Contrary to symmetric-key cryptography where the robustness of the security mechanism relies on a single key being known merely to the sender and receiver, public-key cryptography functions using two separate, but mathematically related keys. Elliptic curve (EC) and ElGamal cryptosystems are two important examples of public-key cryptosystems based totally on finite field arithmetic. Elliptic Curve (EC) cryptosystem is the most efficient public key cryptographic system used in practice. The capability of establishing equivalent security levels with shorter key sizes makes EC cryptosystems appealing for a variety of applications. However, it is computationally intensive and has considerably higher power consumption compared to non-public key cryptosystems. Realization of EC cryptosystems are often described as a hierarchy of operations in which finite field arithmetic operations form the bottom-most layer of the hierarchy. Finite field multiplication is a key operation used in all cryptosystems relied on finite field arithmetic as it not only is computationally complex but also one of the most frequently used finite field operations. The works reported in this dissertation mainly focus on the efficient computation and implementation of finite field multipliers from a hardware implementation point of view. Different digit-level architectures over binary extension field are explored and practical size multipliers for cryptographic applications have also been realized in hardware using 65nm CMOS technology. It is shown that the proposed architectures are more efficient compared to similar proposals considering area/delay complexities as a measure of performance. The second part of this dissertation focuses on custom-layout implementation of highly regular multiplier architectures. To reach higher operating frequency, the main building block of the multipliers are re-designed and realized in domino logic. To alleviate the high power consumption problem associated with domino circuits, a new transistor-level design is developed. It is shown that the proposed implementation can significantly improve the maximum operating frequency of the multiplier in comparison to static CMOS counterpart while consuming even marginally less power. The proposed design methodology can be utilized to achieve higher performances in finite field multipliers with regular architectures.