Date of Award


Publication Type

Master Thesis

Degree Name



Computer Science


Computer Science.




Traditional logic minimization techniques have attempted to minimize a circuit in terms of logic gates. For example, PLAs require minimization of a function in terms of AND columns and OR columns. Synthesis with standard cell also involves minimization in terms of standard gates such as NAND, NOR, inverters etc. However, such minimization at gate level (or even at the transistor level) do not necessarily lead to the most efficient VLSI realizations since the logic gate model does not reflect the restrictions of actual placement and routing in a VLSI circuit. A graph-theoretic model has already been proposed by the VLSI research group of University of Windsor, which is isomorphic to a realizable VLSI structure. It has been recognized that reducing the transistor count does not necessarily minimize the layout area and that the cost of routing wires is also vitally important. Therefore, taking into account the routing complexity in the VLSI array, the goal has been to manipulate the graph-based model to achieve area-optimized, multi-level CMOS VLSI circuits. In this thesis, we have implemented the graph theoretic model in the paradigm of logic programming and developed a topological layout generator based on that model and thereby demonstrated the feasibility of its application to the realistic ASIC design problems. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1993 .D37. Source: Masters Abstracts International, Volume: 32-06, page: 1666. Thesis (M.Sc.)--University of Windsor (Canada), 1993.