Date of Award


Publication Type

Master Thesis

Degree Name



Electrical and Computer Engineering

First Advisor

Chen, Chunhong


Combinational Circuit, Digital, Reliability



Creative Commons License

Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License.


With increasingly high density, today’s integrated circuit chips become sensitive to minor effects such as temperature and environmental noises, which may lead to unreliable operation. While circuit reliability can be improved at various design levels, this usually requires additional costs (such as more area and/or more power consumption). For large-scale circuits, the first step towards reliability improvement is to do reliability estimation efficiently and accurately. This is followed by reliability optimization for given cost or budget constraints, which can be done either locally or globally. In this thesis, we propose an asymmetrical reliability model (ARM) to do quick reliability estimation with a high level of accuracy, in comparison with true reliability values produced by Monte-Carlo simulations. Thanks to its linear-time complexity, this model can be well applied to large-scale circuits. For instance, for benchmark circuit C7552 with 3512 logic gates, it only takes a few seconds to estimate the circuit output reliability with an average error of as low as 0.5%. The only shortcoming of ARM model is that error-free signal probabilities are assumed to be available, which may not always be the case. This motivates us to develop another method to estimate both upper and lower bounds of circuit reliability regardless of signal probabilities. It is also found that the actual average output reliability is strongly correlated with the average upper bound of reliability. This allows us to do fast analysis on circuit reliability with different gate reliabilities, and to develop an efficient gate reliability allocation algorithm which assigns specific reliabilities to individual gates with considerations of given budget constraints. All these methods are verified through simulation results with benchmark circuits.