Date of Award
Electrical and Computer Engineering
Applied sciences, Built-in self-test, Design for test, Hardware security, Linear feedback shift register, Scan-based
Dr. Rashid Rashidzadeh
Dr. Majid Ahmadi
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Scan based Design for Test (DfT) schemes have been widely used to achieve high fault coverage for integrated circuits. The scan technique provides full access to the internal nodes of the device-under-test to control them or observe their response to input test vectors. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation by various attacks. In this work, new methods are presented to protect the security of critical information against scan-based attacks. In the proposed methods, access to the circuit containing secret information via the scan chain has been severely limited in order to reduce the risk of a security breach. To ensure the testability of the circuit, a built-in self-test which utilizes an LFSR as the test pattern generator (TPG) is proposed. The proposed schemes can be used as a countermeasure against side channel attacks with a low area overhead as compared to the existing solutions in literature.
Mehta, Ankit, "A Hardware Security Solution against Scan-Based Attacks" (2016). Electronic Theses and Dissertations. 8002.