Date of Award

3-2-2021

Publication Type

Master Thesis

Degree Name

M.A.Sc.

Department

Electrical and Computer Engineering

First Advisor

Chunhong Chen

Keywords

Circuit reliability analysis, Combinational logic circuits, VLSI

Rights

info:eu-repo/semantics/openAccess

Creative Commons License

Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License.

Abstract

With the continuous scaling of CMOS technologies, integrated circuits are becoming more sensitive to process variations and/or external factors such as temperature or background noise and, as a result, may operate unreliably. Circuit reliability can, however, be improved by making some design changes, and this requires an efficient and accurate method for evaluation of the reliability during the design stage. Reliability of a circuit can be estimated using either simulation-based or analytical based methods. While simulation-based methods (such as Monte-Carlo Simulation) can produce near to perfect estimated values, it takes a long time to run and the run-time increases exponentially with circuit size. On the other hand, analytical methods are relatively fast, but their accuracy level could decrease significantly if signal correlations are not properly accounted for. In this thesis, a new method for calculating the signal reliability correlation coefficient is presented. The proposed method takes advantage of the local information available in the circuit. It is assumed that all signal probabilities of error-free circuits are already available. The proposed method to calculate the Correlation Coefficient was tested for its efficiency and accuracy by applying it on large circuits in comparison with the results produced by the Monte-Carlo Simulation. For circuits containing thousands of gates, their output reliability and probability can be calculated using the proposed method within minutes, as opposed to over 10 hours using Monte-Carlo Simulation. The average errors are as low as 1.67% when all gate reliability is set at 0.95. Throughout the thesis, various ISCAS85 benchmark circuits have been tested under different conditions such as different gate reliabilities, input signal probability and input signal reliabilities in comparison with Monte-Carlo Simulation in order to verify its validity.

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