Date of Award


Publication Type


Degree Name



Electrical and Computer Engineering

First Advisor

A. Ahmadi

Second Advisor

B. Shahrrava


Autocorrelation, Chaotic system, FPGA, Genesio-Tesi, Hardware design, NIST tests




This work presents digital implementation of integer and fractional order Genesio-Tesi chaotic system. In the proposed work, digital hardware design of the model is realized. The model is first validated through software simulations and then translated into Verilog code. Each coefficient is represented through signed 2’s complement fixed point representation. A methodology has been developed to construct integer and fractional order Genesio-Tesi system. Statistical analysis like Maximum Lyapunov Exponent and autocorrelation are employed to quantify the chaotic behavior of the system. Chaotic characteristics have been analyzed by plotting graphs for different set of initial conditions thereby verifying the sensitivity of the Genesio-Tesi system to initial conditions and system parameters. Further, the hardware implementation analysis of the system is carried out on the basis of hardware resource utilization. The hardware and software generated random numbers are compared with each other and the percentage error between them is within 7.5%. The randomness of the fractional order system is verified by NIST statistical analysis and the proposed architecture satisfies all the tests. The NIST results have also been compared with other works.

Available for download on Friday, June 07, 2024