Date of Award
Fall 2021
Publication Type
Dissertation
Degree Name
Ph.D.
Department
Electrical and Computer Engineering
Keywords
SRAM memory devices, Leakage reduction, Low-power applications
Supervisor
H. Wu
Supervisor
B. Balasingam
Rights
info:eu-repo/semantics/openAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.
Abstract
The explosive growth of battery-operated devices has made low-power design a priority in recent years. In high-performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic component, and its relevance increases as technology scales. These trends are even more evident for SRAM memory devices since they are a dominant source of standby power consumption in low-power application processors. The on-die SRAM power consumption is particularly important for increasingly pervasive mobile and handheld applications where battery life is a key design and technology attribute. In the SRAM-memory design, SRAM cells also comprise the most significant portion of the total chip. Moreover, the increasing number of transistors in the SRAM memories and the MOSs' increasing leakage current in the scaled technologies have turned the SRAM unit into a power-hungry block for both dynamic and static viewpoints. Although the scaling of the supply voltage enables low-power consumption, the SRAM cells' data stability becomes a major concern. Thus, the reduction of SRAM leakage power has become a critical research concern.
To address the leakage power consumption in high-performance cache memories, a stream of novel integrated circuit and architectural level techniques are proposed by researchers including leakage-current management techniques, cell array leakage reduction techniques, bitline leakage reduction techniques, and leakage current compensation techniques. The main goal of this work was to improve the cell array leakage reduction techniques in order to minimize the leakage power for SRAM memory design in low-power applications.
This study performs the body biasing application to reduce leakage current as well. To adjust the NMOSs' threshold voltage and consequently leakage current, a negative DC voltage could be applied to their body terminal as a second gate. As a result, in order to generate a negative DC voltage, this study proposes a negative voltage reference that includes a trimming circuit and a negative level shifter. These enhancements are employed to a 10kb SRAM memory operating at 0.3V in a 65nm CMOS process.
Recommended Citation
Rezaei, Neda, "Design and Implementation of Low Power SRAM Using Highly Effective Lever Shifters" (2021). Electronic Theses and Dissertations. 8886.
https://scholar.uwindsor.ca/etd/8886