High Radix and Efficient Hardware Implementation of Modular Integer Multiplication for IoT Cryptosystems
Date of Award
Electrical and Computer Engineering
Field-programmable gate array, Computation process, Clock frequency, IoT, Embedded devices
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This thesis presents a new design for a radix-4 Montgomery Modular Multiplier that is based on field-programmable gate array (FPGA) implementation. This work is an improvement of the radix-4 Montgomery Modular Multiplier structure that requires no multiplication or subtraction operations in the computation process, resulting in a reduced critical path delay and increased maximum frequency. The proposed Montgomery modular multiplication design was implemented on Virtex-7 FPGA platform. The final result shows that this work runs one complete modular multiplication for 256-bit operands, in 0.566 µs with maximum clock frequency of 256.5 MHz by consumption of 4534 number of lookup tables (LUTs). A key feature that also distinguishes the proposed design from the related works is pertinent to adoption of the Kogge-Stone Adder which enhanced the execution frequency and the amount of final throughput of design. This efficient design is compact, making it suitable for systems with limited resources, like lightweight public-key cryptographic and embedded devices in IoT.
Pakzadalinodehi, Fahimeh, "High Radix and Efficient Hardware Implementation of Modular Integer Multiplication for IoT Cryptosystems" (2023). Electronic Theses and Dissertations. 9090.