A PVT resistant coarse-fine time-to-digital converter

Document Type

Conference Proceeding

Publication Date

9-25-2017

Publication Title

Proceedings - IEEE International Symposium on Circuits and Systems

Keywords

high-resolution time interval measurement, PVT resistant, time-to-digital converter (TDC), Vernier TDC

Abstract

This paper presents a fine-coarse time interval measurement scheme which is resilient to the variations of process, voltage, and temperature (PVT). Two Delay Locked Loops (DLLs) have been utilized to minimize the effects of PVT on the measured time intervals. A two-step time-to-digital converter is designed to ensure a high-resolution measurement over a wide dynamic range. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using ADS tools indicate that the measurement resolution varies by less than 0.12ps with ±15% variations of power supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement resolution changes by few femto-seconds from slow to fast corners for process variations and it varies by a maximum of 0.1ps with changes from -40 °C to +100 °C in temperature.

DOI

10.1109/ISCAS.2017.8050742

ISSN

02714310

ISBN

9781467368520

Link to Full Text

Share

COinS