Date of Award
2012
Publication Type
Master Thesis
Degree Name
M.A.Sc.
Department
Electrical and Computer Engineering
Keywords
Computer engineering.
Supervisor
Khalid, Mohamed (Electrical and Computer Engineering)
Rights
info:eu-repo/semantics/openAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Abstract
Currently, FPGAs serve as Field–Programmable–Systems–on–Chip (FPSoCs) and are widely used to implement computationally intensive applications. As the number of components in FPSoCs increases, the interconnect schemes based on Network–on–Chip (NoC) approach are increasingly used. Routers greatly impact the performance and cost of NoCs. In this thesis, we explore the design space of FPGA–based NoC routers. We implement three types of packet switched NoC routers on a Stratix II FPGA using parameterized VHDL models. To reduce the area and increase the speed, we use novel techniques. Buffer size is decreased by minimizing the number of control fields in a packet. Both edges of the clock are utilized, and credit based flow control is used to accelerate the router. The proposed routers were evaluated based on area, frequency, and zero load latency. Synthesis results and zero load latency evaluations show that they are significantly superior to widely referenced, previously proposed routers.
Recommended Citation
Imbewa, Abdelrazag, "Design Space Exploration of FPGA-Based NoC Routers" (2012). Electronic Theses and Dissertations. 123.
https://scholar.uwindsor.ca/etd/123