Date of Award

1995

Publication Type

Master Thesis

Degree Name

M.A.Sc.

Department

Electrical and Computer Engineering

Keywords

Engineering, Electronics and Electrical.

Supervisor

Jullien, G. A.

Rights

info:eu-repo/semantics/openAccess

Abstract

This thesis presents the architecture and the algorithm of the Hierarchy for Pattern Extraction (HyPE) artificial neural network. The training algorithm and the recalling algorithm of the HyPE artificial neural network are rewritten into C based on a Smalltalk prototype. A switching tree minimization program is introduced that provides logic minimization capable of handling a higher transistor tree height and merges several transistor trees. The Northern Telecom 0.8$\mu$ Bipolar Complementary Metal Oxide Semiconductor (BATMOS) technology is used to implement the designs in this thesis. There are two final dynamic neuron designs that have been verified and fabricated. One neuron uses the True Single Phase Clocking (TSPC) Latch and the other neuron uses the Ultra Fast Dynamic Current Steering (UCDCS) latch at the output of the dynamic functional block. The verification of the functional blocks for both neuron designs is done using SPICE simulation. The highest clocking speed applied to the TSPC neuron and the UCDCS neuron are 50MHz and 66MHz, respectively. Additionally, by isolating one of the transistor trees from the functional block, the clocking speed up to 333MHz can be achieved. Finally, a test chip including these two final dynamic neuron designs has been fabricated.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1995 .H86. Source: Masters Abstracts International, Volume: 34-06, page: 2439. Adviser: G. A. Jullien. Thesis (M.A.Sc.)--University of Windsor (Canada), 1995.

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