Date of Award

1996

Publication Type

Master Thesis

Degree Name

M.A.Sc.

Department

Electrical and Computer Engineering

Keywords

Engineering, Electronics and Electrical.

Supervisor

Jullien, G. A.

Rights

info:eu-repo/semantics/openAccess

Abstract

In this thesis, recently developed concepts and circuit design techniques associated with Enhanced Multiple-Output Domino Logic (EMODL) are explored for the design of high performance dynamic carry lookahead adders (CLAs). In order to improve the area and speed of the EMODL design techniques, we investigate the trade-off between the number of cascaded gate stages and the gate fan-in of each stage by varying these factors in four different architectural structures for a 32-bit CLA. From HSPICE simulation results, which show that the number of cascaded stages is a more critical factor than the gate fan-in, a three stage 32-bit dynamic CLA is designed and fabricated in a 1.2$\mu$ CMOS technology. Both HSPICE simulation and test measurements show a critical path of 2.7ns. In comparison with a recent design reported by Hwang and Fisher, which requires five stages, our new architecture demonstrates improved area-speed performance.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1995 .W36. Source: Masters Abstracts International, Volume: 34-06, page: 2446. Adviser: G. A. Jullien. Thesis (M.A.Sc.)--University of Windsor (Canada), 1996.

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