Date of Award

1993

Publication Type

Master Thesis

Degree Name

M.A.Sc.

Department

Electrical and Computer Engineering

Keywords

Engineering, Electronics and Electrical.

Supervisor

Jullien, G. A.

Rights

info:eu-repo/semantics/openAccess

Abstract

This thesis describes a new method of designing multiple output dynamic logic suitable for an automatic synthesis procedure. A new cascode voltage switch logic synthesis method is derived with examples demonstrating the procedures. The procedures are summarized into 3 reduction rules. This method is modified to synthesize multiple output domino logic. A companion algorithm for handling "Don't care cases" is also developed. Another algorithm for transforming a non-planar circuit into a planar circuit for use in automatic layout synthesis is presented. An alternate method of realizing cascode voltage switch logic is developed. It is a semi-custom cell design method. The cell uses almost one half the number of the transistors used in a full tree implementation. All of the new synthesis procedures are automated by a program written in PROGRAPH and C. A SRT self-timed divider is implemented to demonstrate the use of the new procedures. It is implemented in 3$\mu$m CMOS technology.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1993 .C455. Source: Masters Abstracts International, Volume: 32-02, page: 0679. Adviser: G. A. Jullien. Thesis (M.A.Sc.)--University of Windsor (Canada), 1993.

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