"Hardware realization of real-time two-dimensional IIR filters for broa" by Herbert Joseph. Kaufman

Date of Award

1994

Publication Type

Doctoral Thesis

Degree Name

Ph.D.

Department

Electrical and Computer Engineering

Keywords

Engineering, Electronics and Electrical.

Supervisor

Sid-Ahmed, M. A.,

Rights

info:eu-repo/semantics/openAccess

Abstract

In this dissertation, architectures, hardware design and prototypes for the realization of 2-D filters are presented. These filtering architectures are capable of attaining real-time processing rates for advanced television systems and are economical in terms of hardware cost, fabrication cost, and power consumption. Sample-and-hold type realizations, operating on 2-D sampled data, based on the standard 2-D discrete-time transfer function H($z\sb1,z\sb2)$ are presented. Both IIR and FIR realizations are developed in terms of high-speed systolic architectures. The design process culminates in the development of a 2 x 2 recursive prototype. Instead of using the standard discrete-time transfer function it is also possible to develop 2-D filters based on a 2-D hybrid transfer function H(z,s) which involves both z-domain and s-domain variables. These are highly suitable for filtering a raster scanned image, which can be characterized as an input signal X(z,s), which is a function of these same two variables. Design considerations are presented which culminate in the development of a 1 x 1 recursive prototype. The sample-and-hold systolic architecture was employed together with switched-capacitor circuit techniques to develop a 2-D real-time switched-capacitor recursive filter. This type of filter features greater accuracy than a conventional analog circuit as well as advantages for VLSI implementation. In addition to presenting novel design methodologies for hardware prototypes, a novel function block approach for the SPICE simulation of 2-D modular systems with true 2-D data is provided. This approach will serve to greatly facilitate 2-D filter development and improve the efficiency of the design cycle.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1993 .K389. Source: Dissertation Abstracts International, Volume: 56-01, Section: B, page: 0423. Adviser: M. A. Sid-Ahmed. Thesis (Ph.D.)--University of Windsor (Canada), 1994.

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