VLSI design of RNS systolic arithmetic units for high speed digital signal processing applications.

Author

Khosrow. Vojdani, University of Windsor

Date of Award

1987

Publication Type

Master Thesis

Degree Name

M.A.Sc.

Department

Electrical and Computer Engineering

Keywords

Engineering, General.

Rights

info:eu-repo/semantics/openAccess

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.

Abstract

Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1987 .V643. Source: Masters Abstracts International, Volume: 40-07, page: . Thesis (M.A.Sc.)--University of Windsor (Canada), 1987.

Recommended Citation

Vojdani, Khosrow., "VLSI design of RNS systolic arithmetic units for high speed digital signal processing applications." (1987). Electronic Theses and Dissertations. 4535.
https://scholar.uwindsor.ca/etd/4535