A 2-digit multidimensional logarithmic number system filterbank processor for a digital hearing aid.
Date of Award
2003
Publication Type
Master Thesis
Degree Name
M.A.Sc.
Department
Electrical and Computer Engineering
Keywords
Engineering, Electronics and Electrical.
Supervisor
Jullien, G. A.
Rights
info:eu-repo/semantics/openAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Abstract
This thesis addresses the design, implementation, and evaluation of a filterbank for digital hearing aids using a Multidimensional Logarithmic Number System (MDLNS). Hearing loss is a function of both frequency and input level. In a typical digital hearing instrument, the hearing loss compensation is performed by separating the incoming sound into several frequency bands which are then compressed to allow the amplification of low level signals while maintaining the amplitude of high level signals. The demands of low power consumption and small size have led to a number of advances in algorithms, semiconductor technologies and system architectures for completely-in-canal (CIC) hearing aid device. Based on research for digital hearing aids that started in the early 1990's, we have developed a new number system (MDLNS) and associated architecture that benefit the digital hearing aid processor in both of these requirements. Although the LNS has been previously considered for digital hearing aid processors, this thesis presents an exploration of the MDLNS for digital hearing aid circuitry. As with the LNS, the MDLNS provides a reduction in the size of the number representation, but the MDLNS promises a lower cost (area.power) implementation of the arithmetic operations required in both the linear and non-linear domains of filtering and compression. In this thesis we discuss an application of the MDLNS on the construction of a finite impulse response FIR filterbank, a major component of digital hearing aid processors. The MDLNS filterbank processor chip was fabricated using a 0.18 micron CMOS technology. After evaluating the MDLNS filterbank and the two state-of-the-art filterbanks using classic binary implementation, we found power, area, and performance of the MDLNS filterbank processor showed competitive results compared to those binary filterbank processors.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2003 .L5. Source: Masters Abstracts International, Volume: 42-02, page: 0647. Adviser: G. A. Jullien. Thesis (M.A.Sc.)--University of Windsor (Canada), 2003.
Recommended Citation
Li, Hongbo (Jennifer)., "A 2-digit multidimensional logarithmic number system filterbank processor for a digital hearing aid." (2003). Electronic Theses and Dissertations. 515.
https://scholar.uwindsor.ca/etd/515