Date of Award
2016
Publication Type
Master Thesis
Degree Name
M.Sc.
Department
Electrical and Computer Engineering
Keywords
reliability, reliability analysis, signal correlations, The improved equivalent reliability model, The improved Monte Carlo simulation, Three-point method
Supervisor
Chen, Chunhong
Rights
info:eu-repo/semantics/openAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Abstract
Reliability of logic circuits is becoming one of important concerns in the modern integrated circuit design. A large number of inputs and signal correlations make reliability analysis of logic circuits computationally expensive. Many reliabilities analysis approaches have been proposed. Monte-Carlo simulation usually requires hours to obtain a high precision result. Probabilistic gate models (PGM) just work perfectly for small circuits or correlation-free circuits. Probability transfer matrices (PTM) and Bayesian network techniques can give the accurate evaluations, but may become very time-consuming and intractable for larger circuits. This thesis presents three new methods of reliability analysis for large-scale circuits: (1) The improved equivalent reliability model (2) Three-point method (3) The improved Monte Carlo simulation. They can increase the evaluation efficiency and accuracy compared to the other existing approaches. These results are supported by extensive simulations.
Recommended Citation
Cai, Jinchen, "Speeding up Reliability Analysis for Large-scale Circuits" (2016). Electronic Theses and Dissertations. 5804.
https://scholar.uwindsor.ca/etd/5804