Date of Award
2003
Publication Type
Master Thesis
Degree Name
M.A.Sc.
Department
Electrical and Computer Engineering
Keywords
Engineering, Electronics and Electrical.
Supervisor
Miller, W. C.,
Rights
info:eu-repo/semantics/openAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Abstract
This thesis presents the development of an Intellectual Property (IP) core for a System-on-Chip (SoC) implementation of an integrated circuit tester. The resulting realization is called a Tester-on Chip (ToC). The ToC IP core is used in conjunction with a microelectromechanical (MEMS) interface that provides the necessary connectivity between the tester circuitry and the Device Under Test (DUT). Instead of using traditional Automatic Test Equipment (ATE) that includes a complex external test head, the DUT is placed in a MEMS fixture or socket and spring loaded MEMS contacts are used to probe the DUT as required. The ToC implementation can generate and apply a comprehensive set of test vectors at-speed. The resulting test response information is analyzed by the ToC and the corresponding test results are sent via a Universal Serial Bus (USB) interface to a host computer, such as a laptop computer, for visualization and decision making. A scalable vector RAM is used to store the test vectors and it is held as a separate module in the MEMS interface socket. (Abstract shortened by UMI.)Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2003 .R37. Source: Masters Abstracts International, Volume: 42-02, page: 0649. Adviser: W. C. Miller. Thesis (M.A.Sc.)--University of Windsor (Canada), 2003.
Recommended Citation
Rashidzadeh, Rashid., "A digital tester architecture for a system-on-chip implementation." (2003). Electronic Theses and Dissertations. 598.
https://scholar.uwindsor.ca/etd/598
