Date of Award

10-5-2017

Publication Type

Master Thesis

Degree Name

M.A.Sc.

Department

Electrical and Computer Engineering

Supervisor

Chen, Chenhong

Rights

info:eu-repo/semantics/openAccess

Abstract

Rapid progress in the fabrication technology of silicon nano devices has pushed the device dimension toward 1- 100nm length scale, which renders the basic working principles of CMOS devices more dependent upon quantum effects and doping fluctuations. When device dimensions are scaled down to a few nanometers, quantum effects such as single electron tunneling (SET) and energy quantization lead to interesting new device characteristics that can be exploited to create extremely compact circuits. The SET is one type of nanoscale electronic devices based on quantum tunneling and Coulomb blockade effect, where one or more Coulomb islands are sandwiched between two tunnel junctions which connect respectively with the drain electrode and the source electrode, and are capacitively coupled with one or more gate electrodes. However, both pure SET devices and hybrid SET-MOS circuits face a big problem – the background charges, which influence the accuracy of the circuit. In order to improve their immunity against these charges, we introduce the neuron network ‘Boltzmann machine’ into the circuit. This idea is to improve the accuracy with increasing time redundancy. Single-electron circuits show stochastic behaviors in their operation because of the probabilistic nature of electron tunneling phenomena. They can therefore be successfully used for implementing the stochastic neuron operation of Boltzmann machines. This thesis proposes applications of Boltzmann machine network to improve the immunity of hybrid SET/MOS circuits to overcome random background charges. Detailed unit neuron block and whole neuron network model are used to design hybrid SET/MOS circuits. Two applications based on Boltzmann machine are proposed: (1) Multi-bit A/D converter, and (2) One-bit full adder. Simulation was done using Cadence Spectre simulator with 180nm CMOS model and SET MIB macro model for performance evaluation. And it is expected that our idea can be extended to other hybrid SETMOS.

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