Date of Award

1999

Publication Type

Doctoral Thesis

Degree Name

Ph.D.

Department

Electrical and Computer Engineering

Keywords

Engineering, Electronics and Electrical.

Supervisor

Miller, William C.,

Rights

info:eu-repo/semantics/openAccess

Abstract

This thesis introduces a novel approach to the design of circuits found in a very large scale integration (VLSI) implementation of an artificial neural network. A robust hybrid architecture with analog and digital elements has been developed for a fully-parallel single-chip realization of multilayer neural networks. The proposed architecture is highly modular and creates regular silicon structures that well suit a VLSI realization. The architecture employs an innovative universal building block consisting of an improved digital-analog multiplier, a new analog active nonlinear resistor and a digital weight register. The key circuit called a unified synapse-neuron allows one to realize a self-scaling sigmoidal neuron characteristic that does not have to be constantly redesigned to accommodate a varying dynamic input range that is dependent upon the number of synaptic weights connected to the input of the neuron. The effects of synaptic weight quantization noise are also shown to be reduced using a stochastic model developed in the thesis. A new resistive-type neuron circuit is presented that exhibits inherently low characteristic variations based on analyses, simulations and fabrication measurements. Moreover, as each neuron is realized by a number of compact sub-neurons that are distributed over the die area, the effects of process variations on the neuron's characteristics are minimized due to the distributed averaging effect that takes place. Increased robustness is achieved as there is a simultaneous reduction of both digital quantization effects and analog variation effects. The distributed nature of the analog neuron also has the potential to contribute to increased fault tolerance for certain types of neuron circuit failure. Circuit design, implementation and characterization are performed in a standard CMOS process at 5V and 3.3V supply voltages so as to lead to an optimized design. The purpose for this research was to develop a smart non-contact optical sensor based on a programmable neural network with an integrated photosensitive array. The theoretical and experimental work has lead to the design and realization of a highly modular and robust neural-based smart CMOS sensor with reduced interconnection areas and increased synaptic density. As a result, a larger photosensor array and a larger neural network classifier are implemented on a restricted die area. Both theoretical and experimental results are presented in the thesis. Source: Dissertation Abstracts International, Volume: 61-09, Section: B, page: 4877. Adviser: William C. Miller. Thesis (Ph.D.)--University of Windsor (Canada), 1999.

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