Date of Award
2010
Publication Type
Master Thesis
Degree Name
M.A.Sc.
Department
Electrical and Computer Engineering
Keywords
Applied sciences
Supervisor
Maher Sid-Ahmed
Supervisor
Rashid Rashidzadeh
Rights
info:eu-repo/semantics/openAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Abstract
The objective of this thesis is to investigate the applicability of Field Programmable Gate Arrays (FPGAs) for frame delay implementation. FPGAs are programmable devices that can be directly configured by the end user without the use of an integrated circuit fabrication facility. They offer the designer the benefits of custom hardware, eliminating high development costs and manufacturing time. Frame delays are easier to realize using R/W memory where data is written into the memory and read out for each frame. FPGAs are used in a Quartus II environment as it is easy to perform frame delay implementation using schematic entry procedure. Since FPGAs use look-up tables as configurable logic blocks, they are considered as an appropriate choice for frame delay based designs.
Recommended Citation
Afrifa, Kwasi Gyening, "FPGA implementation of a frame delay" (2010). Electronic Theses and Dissertations. 7913.
https://scholar.uwindsor.ca/etd/7913