Date of Award


Publication Type


Degree Name



Electrical and Computer Engineering


Elliptic Curve Cryptography;Field Programmable Gate Array;Finite Field Arithmetic;Hardware Security;Polynomial Multiplication


Mitra Mirhassani


Mohammed Khalid



Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.


Encryption and decryption have been integrated into all communication devices, and Elliptic Curve Cryptography (ECC) has been widely used as a prominent protocol in data security. In ECC, polynomial multiplication has been considered the most time and area-consuming operation, which impacts the overall system’s efficiency. Multiplication algorithms with sub-quadratic computational complexity are widely used to reduce area requirements and improve the delay of ECC cryptographic hardware. This thesis presents new and improved designs for multipliers used in ECC. Firstly, composite multipliers were designed using the M-term Karatsuba and school-book multiplication algorithms. These implementations include a pioneering and novel adaptation of the theoretical model of the M-term Karatsuba multiplication algorithm into a hardware implementation. Secondly, novel binary polynomial multipliers have been proposed using M-term overlap-free Karatsuba multiplication (OFKM), where M is 5–8. For further optimization, these hardware designs also use a hybrid approach that combines M-term overlap-free Karatsuba multipliers with two-term splitting to reduce the need for zero-padding in the final recurrent stages. In all the experimental evaluations, reported device utilization and latency indicated that the proposed multipliers are roughly 26% faster and 15% more efficient in terms of the Area–Delay Product (ADP) compared to the existing designs. Finally, based on the Binary method (left to right), an elliptic curve scalar point multiplication processor was presented using a novel adaptation of the proposed multipliers targeting lightweight and high-speed applications. This processor was designed for two National Institute of Standards and Technology (NIST) recommended binary fields such as Federal Information Processing Standards (FIPS-186) B-163 and B-233. The implemented processor presents a reasonable trade-off between speed and area consumption, and the design compares favourably with previous designs in terms of ADP.

Available for download on Friday, December 20, 2024