Date of Award
10-4-2023
Publication Type
Thesis
Degree Name
M.A.Sc.
Department
Electrical and Computer Engineering
Keywords
FPGA;Machine Learning;PUF
Supervisor
Mohammad Khalid
Rights
info:eu-repo/semantics/embargoedAccess
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.
Abstract
Physical Unclonable Function (PUF) is lightweight hardware that provides affordable hardware-based security for electronic devices and systems which can eliminate the use of the conventional cryptographic system which uses large area and storage. The current imminent concern is the vulnerability of PUFs to popular machine learning attacks such as Covariance Matrix Adaptability and Evaluation Strategy (CMA-ES) attacks and Linear Regression (LR) attacks. To address this issue, many PUF models have been proposed to minimize the vulnerability of PUFs to machine learning attacks. Multi PUFs (MPUFs) are one of the popular models used in this domain and have proven to be successful in providing better security. These models demand large resources and possess comparatively inferior PUF metric values. In this thesis, we propose two new MPUF designs, which also incorporate the XOR technique, to provide improved PUF metric values and also decreased resource usage.The proposed MPUF designs were implemented in a Xilinx Artix 7 FPGA. Experimental evaluation results demonstrate that, compared to existing MPUFs, the proposed MPUF designs provide better uniqueness, reliability, and reduced resource consumption.
Recommended Citation
Bonagiri, Sai Preetham, "A New Resource Efficient Multi PUF Design" (2023). Electronic Theses and Dissertations. 9214.
https://scholar.uwindsor.ca/etd/9214