Date of Award

9-27-2023

Publication Type

Dissertation

Degree Name

Ph.D.

Department

Electrical and Computer Engineering

Keywords

Combination AND/XOR gate;Finite field multiplier;Karatsuba algorithm;Single electron transistor

Supervisor

Huapeng Wu

Supervisor

Chunhong Chen

Rights

info:eu-repo/semantics/embargoedAccess

Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

This work studies area-efficient implementation of bit-parallel binary polynomial multiplication and Karatsuba algorithm (KA), which have important applications in error control coding and network security, especially elliptic curve cryptography, among many other areas. All existing works in this respect are based on traditional CMOS technology. Research shows that new nanodevices such as single-electron transistors (SETs) can offer the great potential at device- and technology-level to further improve area cost in many digital applications (especially multiplication), thanks to their unique Coulomb oscillation characteristics. This thesis first proposes hybrid SET-MOS technology to design the XOR networks that are extensively used in polynomial multiplication architectures, with the goal of reducing the total area cost for their implementation. This is done by using a single SET-MOS gate to realize a multi-input XOR operation which would traditionally require multiple CMOS gates. The existing KA architectures are modified and implemented accordingly using SET-MOS XOR gates. Results show that the proposed multiplier can provide around 37% savings in gate count (with a moderate increase in latency) for the multiplier size ranging from 256 to 2048, compared to the best of CMOS-based multipliers. This thesis also presents novel combinational gates using SET-MOS technology in order to obtain combined AND/XOR operations within a single logic gate. This leads to area-efficient implementation for both AND and XOR operations in multiplication architectures, and produces further reduction in gate count. In comparison with the best existing CMOS work, the proposed 2-way and 4-way KA multipliers save around 46% in gate count. While the latency of proposed SET-MOS work is longer than the existing CMOS counterpart, the area-latency product of the former still shows 4% less than that for the latter. The proposed approaches in this thesis not only promise high area efficiency, but also open up new opportunities for general digital applications involving extensive multiplications. This could potentially and significantly improve the way current multiplier architectures and algorithms are designed and implemented.

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