Date of Award

11-23-2023

Publication Type

Dissertation

Degree Name

Ph.D.

Department

Electrical and Computer Engineering

Supervisor

Majid Ahmadi

Supervisor

Arash Ahmadi

Rights

info:eu-repo/semantics/openAccess

Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Further miniaturization in CMOS technology has faced severe challenges, such as increased leakage power and reduced circuit reliability, which has caused fundamental restrictions on advancing efficient computing architecture. These problems can be addressed by the new emerging devices known as memristors owing to their nanoscale size and the ability to integrate with the exciting CMOS technology. Memristors are passive devices with variable resistance. The resistance value will remain constant when no electrical field is applied, giving this device a unique behavior by saving its last state. This unique behavior makes this device very appealing to a wide variety of applications such as memory, neuromorphic systems, analog circuits, digital circuits, and logic design. The primary focus of this thesis is the utilization of memristors in based logic circuit design aiming to serve CMOS transistor scaling limitation problems by exploiting the integration of memory with the computational capabilities within memristor devices in various designs. Memristors have the potential to attract modern CMOS design since they can be fabricated in high density on the top of the silicon layer, which adds new capabilities to CMOS technology to address the challenges it faces with respect to any further scaling-down.In this thesis, an area efficient Memristor-based digital circuits were implemented utilizing the memristive gates in the style of the integral form of the hybrid Memristor-CMOS and the memristor-only covering a number of conventional arithmetic and computational building blocks. As an example, a 4-bit Memristive Up-Down counter has been implemented using the integral form of the hybrid Memristor-CMOS. The proposed counter is realized using four T Flip-Flops (TFF) connected by AND and OR gates. There are two digital signals (UP and DOWN) that control the counting direction. The verification was performed in the Cadence environment and NC-Verilog. The simulation results have illustrated that the Up-Down counter was successfully able to start or stop counting at any logical state and resume its operation from any other desired logic state. The design demonstrates that the hybrid Memristor-CMOS based Up-Down counter requires fewer number of transistors than in a traditional CMOS based Up-Down counter with 34 CMOS devices and 110 memristors. Therefore, the design has a small layout area and shows a reasonable reduction in power consumption and delay. While other Up-Down counter designs that relied on the pure Memristive method "IMPLY" reported less area, this design overcomes the issues of delay and complexity produced by the lengthy operational steps associated with IMPLY-based design. Moreover, this work was extended in Chapter 6 to provide a comprehensive memristive design for a leaky integrate-and-fire (LIF) neuron circuit. The unique about this proposal is the involvement of the memristor devices in every aspect of the design. The newly discovered Memristor device is finding its way into today's circuit design. These memristor-based structures hold promise to provide continued growth and will significantly enhance the speed and power of digital computing beyond Moore scaling while maintaining compatibility with standard CMOS.

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